1. Field of the Invention
The present invention relates to an array of MOS semiconductor devices and a process for forming the array, and in particular, to a ROM array having successive bit lines disposed in vertically separated planes, thereby minimizing the horizontal surface area occupied by the array.
2. Description of the Related Art
FIG. 1 shows a plan view of an NMOS ROM array formed in a single horizontal plane, as disclosed in U.S. Pat. No. 5,590,068 ("the '068 Patent"). FIG. 1A shows a cross-sectional view along line 1A-1A'. FIG. 1B shows a cross-sectional view along line 1B-1B'.
The '068 patent teaches creation of an alternate virtual ground ROM array 100 of data storage cells 102. In FIG. 1, the array is shown as a plurality of NMOS ROM devices formed within lightly doped P-type silicon 114. ROM data storage cells 102 are defined by overlapping of a word line 104 over a pair of diffused bit lines 106. Diffused bit lines 106 actually consist of global diffused bit lines 106a alternating with local diffused bit lines 106b. Local diffused bit lines 106b are grounded and serve as the sources of cells 102 of array 100.
Polysilicon word lines 104 are oriented perpendicular to diffused bit lines 106 and are separated from bit lines 106 by a gate oxide layer 108. Where a polysilicon word line 104 crosses over channel region 110 between successive diffused bit lines 106a and 106b, MOS semiconductor device 102 is formed having local diffused bit lines 106b as the source, global diffused bit line 106a as the drain, word line 104 as the gate, and gate oxide layer 108 as the gate.
Array 100 is divided into segments. Within each segment, the size of each cell 100 can be estimated by the pitches of word lines 104 and diffused bit lines 106. For design rules based upon a pitch of .lambda., the cell size is 4.lambda..sup.2. This calculation is based on an array structure in which all diffused bit lines and cell transistors are disposed in the same horizontal plane.
The ROM array structure disclosed by the '068 Patent is adequate to perform its intended function. However, this ROM structure consumes substantial amounts of surface area of the underlying silicon.
Therefore, there is a need in the art for a ROM array structure and a process for forming such an array structure that is more compact and occupies less silicon surface area.